A correctness oracle for analog IC layout. Pistalogic verifies a layout against a golden schematic and returns PASS / FAIL / UNVERIFIED — never a silent pass. Today the ota_5t single-stage OTA is verified on SkyWater 130nm: DRC + LVS (magic + netgen) plus a 15-corner PVT post-layout (PEX) simulation against foundry models — not silicon — at default sizing. More verified blocks rolling out. Currently invite-only: join the waitlist at pistalogic.com for early access.